Sta Engineer Job in Spectrum Consultants India Pvt Ltd
Sta Engineer
Spectrum Consultants India Pvt Ltd
4+ weeks ago
- Bengaluru, Bangalore Urban, Karnataka
- Not Disclosed
- Permanent
Job Summary
Responsibilities
Develop functional, test constraints from scratch
Identify constraints required beyond traditional/available, provide them as needed
Close constraint coverage loss/issues
Improve PPAS by but not limited to improvements in Methodology, Analysis and ECO
Understand chip level clock, reset architecture and drive easy timing closure
Derive and is accountable for sign-off timing margins
Final reviewer for STA reports before submission to manufacturing
Signal integrity analysis & fix
Do bottleneck analysis, Report abstract data, prioritize fixation methods and identify methods for margin improvement
Coordinate with Full chip Physical design team
Coordinate with RTL design/architecture team
An individual contributor, knows requirements to execute his/her responsibilities and seamlessly drives needed coordination among technical team members to constantly achieve better PPAS
Requirements
A minimum of 13-19 years of Static timing analysis/RTL development/RTL Synthesis experience
Very strong STA fundamentals, Signal integrity fundamentals
The specialist in Synopsys Design Constraints (SDC) constructs, issues, customized constraint delivery specialist
Lower power timing closure methodology experience
Fully aware of different DFT modes, has developed/modified/merged constraints for DFT modes
Specialist in at least one EDA tool, but is tool/methodology/flow agnostic with great functional proven experience
Very good proficiency in at least one programming language like TCL/PERL/Python
Has done at least one multi-partition/multi-million gate System on Chip / Test chip as top level hands-on STA lead.
Leads by example, works on ambitious, results-oriented schedule & does data driven, flawless aligned decision making
Well aware of Silicon development and Post-silicon work flows
Knowledge of abstract timing models, creation of/issue/limitations of.
Excellent debug , analytical skills
Specialist in collaborating in a team of multi-functional, geographically distributed members with highly diverse skill levels.
Bachelors of Engineering/Master of Technology in E&C/Electrical/Computer Science.
Preferred Skills:
Strong verbal, interpersonal skills
Spice simulation experience
Strong electronic circuit fundamentals, Circuit level timing fixes
Post-Silicon timing debug experience
RTL coding/verification experience
P&R implementation exposure
Develop functional, test constraints from scratch
Identify constraints required beyond traditional/available, provide them as needed
Close constraint coverage loss/issues
Improve PPAS by but not limited to improvements in Methodology, Analysis and ECO
Understand chip level clock, reset architecture and drive easy timing closure
Derive and is accountable for sign-off timing margins
Final reviewer for STA reports before submission to manufacturing
Signal integrity analysis & fix
Do bottleneck analysis, Report abstract data, prioritize fixation methods and identify methods for margin improvement
Coordinate with Full chip Physical design team
Coordinate with RTL design/architecture team
An individual contributor, knows requirements to execute his/her responsibilities and seamlessly drives needed coordination among technical team members to constantly achieve better PPAS
Requirements
A minimum of 13-19 years of Static timing analysis/RTL development/RTL Synthesis experience
Very strong STA fundamentals, Signal integrity fundamentals
The specialist in Synopsys Design Constraints (SDC) constructs, issues, customized constraint delivery specialist
Lower power timing closure methodology experience
Fully aware of different DFT modes, has developed/modified/merged constraints for DFT modes
Specialist in at least one EDA tool, but is tool/methodology/flow agnostic with great functional proven experience
Very good proficiency in at least one programming language like TCL/PERL/Python
Has done at least one multi-partition/multi-million gate System on Chip / Test chip as top level hands-on STA lead.
Leads by example, works on ambitious, results-oriented schedule & does data driven, flawless aligned decision making
Well aware of Silicon development and Post-silicon work flows
Knowledge of abstract timing models, creation of/issue/limitations of.
Excellent debug , analytical skills
Specialist in collaborating in a team of multi-functional, geographically distributed members with highly diverse skill levels.
Bachelors of Engineering/Master of Technology in E&C/Electrical/Computer Science.
Preferred Skills:
Strong verbal, interpersonal skills
Spice simulation experience
Strong electronic circuit fundamentals, Circuit level timing fixes
Post-Silicon timing debug experience
RTL coding/verification experience
P&R implementation exposure
Experience Required :
6 to 15 Years
Vacancy :
2 - 4 Hires
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