Sta/ Timing Engineer Job in Qualcomm Technologies, Inc

Job Description: Hardware Engineer

Company: Qualcomm India Private Limited
Job Area: Engineering Group, Hardware Engineering

General Summary

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drive digital transformation. As a Hardware Engineer at Qualcomm, you will be involved in planning, designing, optimizing, verifying, and testing electronic systems, including circuits, mechanical systems, Digital/Analog/RF/optical systems, test systems, FPGA, and DSP systems. You will collaborate with cross-functional teams to develop solutions that meet performance requirements and launch cutting-edge products.

Minimum Qualifications

• Education:
  • Bachelor s degree in Computer Science, Electrical/Electronics Engineering, or a related field with 4+ years of hardware engineering experience;
    OR
  • Master s degree in Computer Science, Electrical/Electronics Engineering, or a related field with 3+ years of hardware engineering experience;
    OR
  • PhD in Computer Science, Electrical/Electronics Engineering, or a related field with 2+ years of hardware engineering experience.

Responsibilities

• STA Setup & Convergence: Set up, review, and sign off on Static Timing Analysis (STA) for multi-mode, multi-voltage domain designs.
• Timing Analysis: Perform validation and debugging across multiple process, voltage, and temperature (PVT) conditions using tools like PrimeTime and Tempus.
• Flow Optimization: Optimize STA flow and ensure Spice to STA correlation.
• Methodology Development: Evaluate various timing methodologies/tools across different designs and technology nodes; develop automation scripts within STA/Physical Design (PD) tools.
• Technical Communication: Produce clear technical documentation and communicate effectively in a cross-collaborative environment.

Required Experience

• Proficiency in design automation using TCL, Perl, or Python.
• Familiarity with digital flow design implementation from RTL to GDS, using tools like ICC, Innovus, and PT/Tempus.
• Experience with process technology enablement, including circuit simulations using HSPICE or FineSim and Monte Carlo analysis.

Preferred Qualifications/Skills

• Strong expertise in STA timing analysis basics, including AOCV/POCV concepts, clock tree synthesis (CTS), defining and managing timing constraints, and handling latch transparency.
• Hands-on experience with STA tools like PrimeTime and Tempus, including driving timing convergence at the chip and hard-macro levels.
• In-depth knowledge of cross-talk noise, signal integrity, layout parasitic extraction, and feed-through handling.
• Familiarity with ASIC back-end design flows, methods, and tools (ICC2, Innovus).
• Knowledge of spice simulation and silicon to spice model correlation.
• Proficient in scripting languages such as TCL, Perl, and Awk.
• Basic knowledge of device physics.