Io Pads And Esd Layout Engineer [senior] Job in Spectrum Consultants India Pvt Ltd
Io Pads And Esd Layout Engineer [senior]
Spectrum Consultants India Pvt Ltd
4+ weeks ago
- Hyderabad, Telangana
- Not Disclosed
- Permanent
Job Summary
Role and Responsibilities
Responsible for design and development of IO PADS/ESD Layouts and support full chip level integration.
Perform layout verification like LVS/DRC/Latchup, quality check and documentation.
Responsible for on-time delivery of block-level layouts with acceptable quality.
Demonstrate leadership Skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/milestones in multiple project environment.
Guide junior team-members in their execution of Sub block-level layouts & review their work.
Contribute to effective project-management.
Effectively communicating with engineering teams in the US, Japan and China to assure the success of the layout project.
Qualification/Requirements
8+ year experience in IO PADS/ESD layout design in advanced CMOS process.
Strong fundamentals in IO PADS, ESD concepts, wire bond and Flip chip layouts.
Familiar with different structures of IO Pad layouts and ESD structure.
Experience in failure mechanisms like antenna, latch-up, and ESD.
Exposure to Signal Integrity issues like EM and IR drop analyses.
Have worked on high-speed interfaces like DDR, Serdes, MIPI and understand the constraints of high-speed IO layout Design.
Understanding of layout effects on the circuit such as speed, capacitance, power and area etc.,
Ability to understand IO PAD design specifications and implement high-quality layouts.
Excellent command and problem-solving skills in physical verification of custom layout.
Excellent problem-solving skills in solving area, power, performance and physical verification of custom layout.
Experience with Cadence tools including Virtuoso schematic editor Virtuoso layout L, XL & Verification tools like Mentor Calibre- Proficient in Device Matching, Parasitic Analysis, Electron Migration, and Isolation Techniques.
Should have leadership qualities and able to do multi-tasking as required.
Should be able to work in a team environment and able to guide and provide technical support to the fellow team members.
Self-motivated, hardworking, goal-oriented and excellent verbal and written communication skills.
Multiple Tape out support experience will be an added advantage.
Excellent verbal and written communication skills.
Education
BE or MTech in Electronic/VLSI Engineering
(we will also consider exceptionally talented Diploma holders in electronic or VLSI engineering)
Responsible for design and development of IO PADS/ESD Layouts and support full chip level integration.
Perform layout verification like LVS/DRC/Latchup, quality check and documentation.
Responsible for on-time delivery of block-level layouts with acceptable quality.
Demonstrate leadership Skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/milestones in multiple project environment.
Guide junior team-members in their execution of Sub block-level layouts & review their work.
Contribute to effective project-management.
Effectively communicating with engineering teams in the US, Japan and China to assure the success of the layout project.
Qualification/Requirements
8+ year experience in IO PADS/ESD layout design in advanced CMOS process.
Strong fundamentals in IO PADS, ESD concepts, wire bond and Flip chip layouts.
Familiar with different structures of IO Pad layouts and ESD structure.
Experience in failure mechanisms like antenna, latch-up, and ESD.
Exposure to Signal Integrity issues like EM and IR drop analyses.
Have worked on high-speed interfaces like DDR, Serdes, MIPI and understand the constraints of high-speed IO layout Design.
Understanding of layout effects on the circuit such as speed, capacitance, power and area etc.,
Ability to understand IO PAD design specifications and implement high-quality layouts.
Excellent command and problem-solving skills in physical verification of custom layout.
Excellent problem-solving skills in solving area, power, performance and physical verification of custom layout.
Experience with Cadence tools including Virtuoso schematic editor Virtuoso layout L, XL & Verification tools like Mentor Calibre- Proficient in Device Matching, Parasitic Analysis, Electron Migration, and Isolation Techniques.
Should have leadership qualities and able to do multi-tasking as required.
Should be able to work in a team environment and able to guide and provide technical support to the fellow team members.
Self-motivated, hardworking, goal-oriented and excellent verbal and written communication skills.
Multiple Tape out support experience will be an added advantage.
Excellent verbal and written communication skills.
Education
BE or MTech in Electronic/VLSI Engineering
(we will also consider exceptionally talented Diploma holders in electronic or VLSI engineering)
Experience Required :
8 to 15 Years
Vacancy :
2 - 4 Hires
Similar Jobs for you
Help us improve TheIndiaJobs
Need Help? Contact us