Asic Design Manager Job in Sinergia Media Labs Is A Private Limited

Asic Design Manager

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Job Summary

Roles and Responsibilities

  • Responsible for RTL Design and Integration of complex digital IPs and ASICs
  • Bachelor's degree in Electrical/Computer Engineering or Computer Science and 7+ years OR a Master's degree in Electrical/Computer Engineering or Computer Science and 5+ years of experience in Design of ASIC, custom ICs, and/or FPGAs
  • Define micro-architecture specifications, technical proposals, logic design and RTL
  • Assist verification team in developing Test plan and test coverage
  • Review coverage reports from regression tests and provide feedback to verification team
  • Assist post-silicon validation team in platform debugging
  • Assist physical design team in floorplan and static timing
  • Performs logic design, Register Transfer Level RTL coding, and drives imulation/emulation to make sure quality of the IP
  • Interact and participate in discussion with customer on IP integration and reviews Qualifications: Hands on Experience with designing complex IP and SoC Experience in AXI, DDR4, HBM, PCIe design is a plus Must have multiple tape-out and Silicon bring-up experience Experience in design of hardware accelerators, co-processors, memory controllers is a

The Ideal Candidate

  • Hands on Experience with designing complex IP and SoC
  • Experience in AXI, DDR4, HBM, PCIe design is a plus
  • Must have multiple tape-out and Silicon bring-up experience
  • Experience in design of hardware accelerators, co-processors, memory controllers is a plus
  • Experience coding within Verilog and/or System Verilog along with scripting languages such as Perl, Tcl, or Python
  • Hands-on experience on Lint/CDC, SDC ownership and qualification, Timing ECO iterations, debugging in mixed-signal simulation environment, etc
  • Experience in cross functional interaction with verification, DFT and physical design teams.
  • Strong understanding of ASIC and/or full custom chip development process with logic design and RTL proficiency is required
  • Experience with FPGA programming is a plus
  • Coherency and computer architecture experience is desirable
Experience Required :

Fresher

Vacancy :

2 - 4 Hires