Senior Position Asic Verification Manager Job in Sinergia Media Labs Is A Private Limited

Roles and Responsibilities

• Drive the test bench architecture, verification plan and test bench development for full chip and subsystem verification.
• Bachelor's degree in Electrical/Computer Engineering or Computer Science and 7+ years OR a Master's degree in Electrical/Computer Engineering or Computer Science and 5+ years of experience in Verification of ASIC, custom IC designs, and/or FPGA designBuild and lead the verification team.
• Mentor and lead a team of verification engineers to complete unit, subsystem and chip level verification.
  
• Develop and maintain methodology, flows, and sign-off criteria for verification.

The Ideal Candidate

• Experience with development of test bench architecture, test plan and test bench development for full chip and subsystem verification
• Hands on experience with System Verilog and VMM/OVM/UVM
• Hands-on experience with simulation tools including Synopsys VCS, Cadence IES to verify full-chip SoCs and FPGA based designs
• Requires strong understanding of state-of-the-art verification techniques, including assertion and metric-driven verification.
• Experience in AXI, DDR4, HBM, PCIe verification is a plus
• Verification experience in hardware accelerators and coprocessors is a plus
• Familiarity with verification management tools including regression management is required
• Familiarity with scripting in Python or Perl
• Strong understanding of ASIC and/or full custom chip development process is required
• Experience with FPGA programming and software is a plus
• Coherency and computer architecture experience is desirable
• Experience with formal property checking tools such as Cadence (IEV), Jasper, and Synopsys (Magellan) is a plus.
• Experience with gate level simulation, power verification, reset verification, contention checking, abstraction techniques are a plus