Design And Verification Engineer Job in Si2chip Technologies Pvt. Ltd

Design And Verification Engineer

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Job Summary
  • Engineer for SOC/ IP level functional verification
  • Perform SOC/ IP level functional verification using SystemVerilog/ UVM
  • Execute test plans, block and chip level test benches using SystemVerlilog (VMM/ UMV) based methodology; achieve complete coverage to ensure first working silicon.
  • Experience in C/ C and Perl/ TclTk languages a plus
  • Verification experience with PCIe/ USB a plus
Experience Required :

4 to 10 Years

Vacancy :

2 - 4 Hires

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