Design Verification Engineer Job in Broadcom

Design Verification Engineer

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Job Summary
  • 5 to 10 years of experience in Verification with BSEE/MSEE.
  • Very good System Verilog/UVM/OVM knowledge with prior work experience on live projects.
  • Expertise in creating detailed test plan with well-defined functional coverage goals.
  • Should be able to architect and implement self - generating / self- checking simulation verification environment to reach functional coverage goals using random/directed stimulus.
  • Knowledge of scripting language like Perl, Shell, TCL or Python.
  • Very Good debugging skills.
  • Should have good documentation/communication skills and be able to work with multi-functional, multi-site teams .
  • Experience in running and debugging Gate level simulations.
  • Successful experience in 802.11 Wireless VLSI designs or other related technologies is a big plus.
  • Knowledge of protocols like AXI and ARM subsystems and top level interconnects is plus.
  • Highly motivated and independent contributor with good aptitude and attitude.
Experience Required :

Fresher

Vacancy :

2 - 4 Hires

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