R&d Engineer Ic Design 4 Job in Broadcom

Job Description:

Job Description:

Broadcom CEG Memory team is looking for a Mutiskilled PNR, STA, RTL and Verification Engineer. The Successful candidate will work in one or more domains of RTL, Verification, PNR, and STA for Complex subsystems of Hierarchical Blocks including BIST. It is great Opportunity for the people who wants to gain in depth knowledge on end to end Chip development flow with Deeper Expertise on DFT and Memory BIST. Need to have minimum 8 years experience with Bachelor degree

Subsystem RTL, PNR, STA Designer

RTL development and Verification for Digital, Memory Subsystems including BIST. RTL to GDS2 flow development and Automation for Complex Digital subsystems including BIST. Static timing analysis, formal verification, Cross Clock Domainchecks, Power/Timing sign off Develop RTL to GDS flow in advanced technology nodes from scratch Verify complex Subsystems through OVM, UVM methodology, creating the Verification Suit Independently. Contribute in developing the complete Netlist to GDS2 automation flow for complex blocks usingPNRtools likeICCor Encounter in 16FF/10FF/7FF Technologies. Define the Floor Plan/placement/routing/Timing constraints inICCfor Complex blocks including Memory BIST to achieve correct by construct DRC/LVS and timing closure Interact with the Cross functional IP teams, Flow teams, (Synthesis/STA/DNE) to close the loop in timing violations/DRC/LVS. ICC/Synthesis/STAconstraints automation to achieve predictable timing closure correct by construct DRC/LVS through automation with minimal randomness.

Skillset:

Hands on Experience with RTL, Synthesis, ICC2, Fusion, Innovus, Prime time tools Hands on experience in definingICC/Synthesis constraints that meets timing closure needs In-depth knowledge of Signal and Power Floor plan with minimal EM/IR violations In-depth expertise with allIC/STAoptions to handle de-ratings, Options to reduce cross talk Hands on expertise with TCL/PERL to automate the end to endPNRflow. Capability to handle a complex Netlist with multiple frequency domains andICCtiming closure. Hands on experience in analyzing and correlatingSTA.vs.ICCtiming reports. Familiarity with ECO flow, Implementing IR drop fixes, Familiar with FinFet technology anddesignrules, SPEF extraction, signal EM, power-EM, Noise analysis and fixes. Knowledge of Synopsys tools (Milky way, Star-RC, Primetime,..) & exposure to cadence tools will be added advantage

Additional Traits:

Highly committed Self-driven Strong Individual with Can do attitude

Work in dynamic environment with high Integrity and assertiveness

Excellent team player with Great Communication skills

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, gender identity, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

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