Digital Design Engineer Job in Vipany
Job Summary
Job Description
Mandatory Skills:
- Knowledge of Verilog and/or System Verilog language for design
- Knowledge and ability to use digital and mixed-signal simulators, logic synthesizer, static timing analysis tools, CDC tools
- Must have good problem-solving skills
- Must have good communication skills and the ability to work efficiently in a team
- Must be self-motivated to produce best quality results
Preferred Skills:
- Experience with digital design for non-volatile memories and mixed signal products
- Knowledge and ability to use testability techniques such as scan test and test pattern generation is a plus
- Experience with UPF flow is a plus
- Knowledge of SVA and UVM methodology
Responsibilities:
- Define architecture of digital blocks in digital and mixed signal products
- Define and implement RTL based design solutions
- Be responsible for synthesis flow and generation of synthesis constraints
- Be responsible for static timing analysis on pre and post routed design, interact with APR team
- Perform CDC analysis
- Perform, analyze and debug block level and full chip simulations using logic simulators, interact with digital and mixed signal verification team
- Support analytical debug of silicon in prototype design phase
Experience Required :
5 to 10 Years
Vacancy :
2 - 4 Hires
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