Ip/soc Logic Design Engineer Job in Tessolve

Qualification: BE/ME/B.Tech/M.Tech in EEE/ECE/EI/CS

Experience: 5 15 years

No of Position: 3

NOTE: This is for ONSITE to US and Valid H1B VISA is Mandatory

Job Description:

• Performs logic design, Register Transfer Level RTL coding, and simulation to generate cell libraries, functional units, and subsystems for inclusion in full chip designs
• Participates in the development of Architecture and Microarchitecture specifications for the Logic components
• Evaluates new feature requests, Designs and develops IP features
• Provides IP integration support to SoC customers and represents RTL team
• Collaborating with cross discipline stake holders in defining micro-architecture, implementing RTL in System Verilog and integrating other IPs into the design