R&d Engineer, Staff Job in Synopsys
R&d Engineer, Staff
Synopsys
4+ weeks ago
- Noida, Gautam Buddha Nagar, Uttar Pradesh
- Not Disclosed
- Full-time
Job Summary
Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.
Synopsys Verification Group is looking for an R&D engineer to work on the compiler for its FPGA-based Prototyping platforms.
Responsibilities:
- Responsible for research and development of logical synthesis, netlist partitioning, placement and routing optimizations.
- Responsible for developing, testing and tuning stable ASIC/FPGA CAD/EDA algorithms targeting high quality of results (QoR) such as area, performance, congestion, compile time and power etc.
- Designs, implements, tests, delivers and maintains highly efficient algorithms and data structures.
- Usually developing professional expertise and may apply company policies and procedures to resolve a variety of issues.
- Exercises judgment to determine appropriate action. Implementations and solutions are reviewed for accuracy and overall adequacy.
- Builds productive internal/external working relationships.
- Contacts are primarily within business unit and occasional organizational and external customer contacts on routine matters.
- PhD or master s degree in electrical and/or Computer Engineering with 5+ years or bachelor s degree with 8+ years of relevant experience.
- Strong C++ and problem-solving skills.
- Original research publications in the area of computer engineering / electronic design and verification field is a big plus.
- Proficiency in designing data structures, algorithms, and specs for sophisticated software products.
- Basic EDA knowledge and experience in areas such logical and physical synthesis, RTL, simulation, emulation, formal verification etc.
- Experience with FPGAs is a plus.
- Background in machine learning is a plus.
- Background in netlist optimizations for area, performance, congestion, power etc.
- Digital IC design flows (ASIC and FPGA)
- Skillful in using script languages such as TCL, Python, Perl, Unix shell scripts.
- Experience with developing software into a large code bases desired
- Familiarity with industrial standard SW development and quality practices.
- Results-driven, agility, integrity and teamwork. Desire to learn and explore unfamiliar concepts, tools and techniques.
- Strong communication skills, verbal and written. Ability to coordinate discussions with other R&D teams.
Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.
Experience Required :
Fresher
Vacancy :
2 - 4 Hires
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