Asic/layout Design Engr, Sr I Job in Synopsys

Thisrole requires the incumbent to contribute towards back-end design forcustomer projects, support in revising and debugging existing products,create relevant documentation for company products, and run product QAand resolve issues thereof. This person will also be required tounderstand the memory compiler development and methodology.

Minimum education and years of experience required:

• BE in EE with 5+ years of experience inmemory full custom layout design.

• MS with 3+ years ofexperience inmemory full custom layout design.

Required skills:

• Knowledge of physical design methodologies/ Physical design phases/ Floor planning, Place and route, physical verification, Signal integrity.

• Memory compiler block placement, power rings and interconnects routing in memory macro .

• IR/EM analysis of memories including back annotation of layout parasitic, physical verification using DRC and LVS tools.

• Workwith moderate supervision. Produce technical designdocuments and maintain accurate and thorough documentation of work. Bea positive participant, cultivator and active team member.

• Apply basic to moderate problem solving skills. Able to do project status reporting.

• Have basic task tracking and self-management skills.

Tools/Languages:

• Layout Design tools (preferably CD) and Schematic capture, DRC LVS Verification Tools (preferably ICV, Hercules), Power analysis Tools (preferably HSIM PWRA)

• Scripting languages (preferably TCL, C-shell, Perl)