Asic Digital Design Engr, I Job in Synopsys

Asic Digital Design Engr, I

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Job Summary

1.Digital RTL development of one or more IPs. Need ability to understand requirements, come-up with micro architecture with guidance & implement with guidance. Domain of work is Serial Interfaces (SERDES & PHY) like USB2/USB3/MIPI/PCIe/Ethernet/JESD. Candidate will fully own the digital design for his IP.
2.The design involves control loops between analog and digital. Candidate needs basic knowledge of control system and basics of primary electrical signals
3.Supporting timing closure by providing constraints, clock tree spec, helping out on critical paths required. Clock speed in design is upto 3GHz. Candidate needs ability to understand timing concepts.
4.Continuous process improvement & automation using perl/tcl or other methods needs candidate to have aptitude for software coding

Experience Required :

Fresher

Vacancy :

2 - 4 Hires

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