Analog Design Engr, Staff Job in Synopsys

[Job Title]
A&MS Ckt Design Engineer Sr2. (ESD & Latchup)
Job Overview
The successful candidate will work on latest FinFet, FDSOI and BCD technologies from leading foundries. Candidate would get responsibility and ownership to create Best-in-Class ESD and LU robust solutions for interface IPs. The person would be responsible from design to silicon qualification of ESD structures carefully chosen to build any design offer for our worldwide customer base.
Responsibilities and Duties

• Ensuring ESD and Latch-up robustness of supply clamps and interface circuits through
  • ESD simulations
  • PERC checks Topo, CD, P2P and LDL
• ESD and Latch up qualification of I/O testchip
  • To ensure testchip configurations which cover all the required verification structures
  • Follow-up with Test Lab by giving them required test instructions
  • Ensuring qualification of requisite number of units for target HBM, CDM and LU specs.

• Providing I/O ring development Rules and review of customer I/O ring

• Providing ESD and LU distance rules for any new technology development offer.
• Analyzing customers, I/O ring configurations.
• Verifying it for all ESD rules and PERC rules compliance.
• Providing timely feedback to customer along with follow-up till its successful tap-out.

• Interaction with Foundry
  • To identify right ESD device structures suitable for Normal or Failsafe interface IPs.
  • Follow-up for suitable ESD models for running ESD simulations
  • Follow-up for Breakdown voltage and TLP/VFTLP data of ESD and victim devices.
• Interact with Design and layout teams and provide timely ESD & LU inputs necessary for robustness of design.
• Analyze customer queries and provide timely answers.

• B.Tech/BE/M.Tech/MS in Electronics Engineering
• 10+ years of overall experience in I/O development and in-depth knowledge of ESD and LU domain.
• Prior experience of I/O ring development/review.
• Good understanding of Interface Testchip development and qualification
• Hands-On experience in running ESD simulations by making ESD network

• To identify right ESD device structures suitable for Normal or Failsafe interface IPs.
• Follow-up for suitable ESD models for running ESD simulations
• Follow-up for Breakdown voltage and TLP/VFTLP data of ESD and victim devices.