Staff Principal Engineer - Sta Job in Spectrum Consultants India Pvt Ltd
Staff Principal Engineer - Sta
Spectrum Consultants India Pvt Ltd
4+ weeks ago
- Hyderabad, Telangana
- Not Disclosed
- Permanent
Job Summary
Job Description
As a Design Engineer in DRAM and Emerging memory Group (DEG), you will be responsible for designing and verifying Functional Blocks used in the development of memory products. This includes simulating, optimizing, and timing analysis when deploying into DRAM circuits. In this position you will work and support the efforts of groups such as DEG Design/Verification to proactively design products that optimize all manufacturing functions and assure the best cost, quality, reliability, time-to-market, and customer satisfaction.
Responsibilities will include, but are not limited to, the following:
Build function and timing models for standardized and customized logic design.
Perform Static Timing Analysis on the memory control logic design with industry lead EDA tools.
Deploy the RTL-IP with the standardized flow and continue improving the flow for high quality.
Supporting the RTL-IP user for layout process including floor-planning, placement, and routing
Perform verification processes with modelling and simulation using industry standard simulators.
Maintain technical expertise and provide training.
Contribute to cross group communication to work towards standardization and group success.
Proactively solicit input from Standards, CAD, modelling, and verification groups to ensure the design quality.
Drive innovation into the future Memory generation with dynamic work environment.
Successful candidates for this position will have:
7-12 years of rich experience in STA and making timing constrains based on Primetime or it s counterparts.
Experience in taking an industrial specification and implementing the respective IP.
Good understanding on timing/area/power/complexity trade-offs on complex interface design
Familiar with IP level verification and strong RTL debugging capabilities.
Experience in frontend implementation tasks such as synthesis and logic equivalence
Experience in large scale mix signal circuitry design including logic implementation/verification, timing analysis/optimization an advantage.
Experience in ASIC backend flow with parasitic extraction and timing closure is a plus.
Experience in liberty/Verilog model characterization is a plus.
Excellent problem-solving and analytical skills.
A self-motivated, enthusiastic team player who enjoys working with others.
Good communication skills with the ability to convey complex technical concepts to other design peers in verbal and written form.
Education (One of the following is required)
A bachelor s in electrical engineering or related discipline plus 9 years of experience.
A master s in electrical engineering or related discipline plus 7 years of experience
As a Design Engineer in DRAM and Emerging memory Group (DEG), you will be responsible for designing and verifying Functional Blocks used in the development of memory products. This includes simulating, optimizing, and timing analysis when deploying into DRAM circuits. In this position you will work and support the efforts of groups such as DEG Design/Verification to proactively design products that optimize all manufacturing functions and assure the best cost, quality, reliability, time-to-market, and customer satisfaction.
Responsibilities will include, but are not limited to, the following:
Build function and timing models for standardized and customized logic design.
Perform Static Timing Analysis on the memory control logic design with industry lead EDA tools.
Deploy the RTL-IP with the standardized flow and continue improving the flow for high quality.
Supporting the RTL-IP user for layout process including floor-planning, placement, and routing
Perform verification processes with modelling and simulation using industry standard simulators.
Maintain technical expertise and provide training.
Contribute to cross group communication to work towards standardization and group success.
Proactively solicit input from Standards, CAD, modelling, and verification groups to ensure the design quality.
Drive innovation into the future Memory generation with dynamic work environment.
Successful candidates for this position will have:
7-12 years of rich experience in STA and making timing constrains based on Primetime or it s counterparts.
Experience in taking an industrial specification and implementing the respective IP.
Good understanding on timing/area/power/complexity trade-offs on complex interface design
Familiar with IP level verification and strong RTL debugging capabilities.
Experience in frontend implementation tasks such as synthesis and logic equivalence
Experience in large scale mix signal circuitry design including logic implementation/verification, timing analysis/optimization an advantage.
Experience in ASIC backend flow with parasitic extraction and timing closure is a plus.
Experience in liberty/Verilog model characterization is a plus.
Excellent problem-solving and analytical skills.
A self-motivated, enthusiastic team player who enjoys working with others.
Good communication skills with the ability to convey complex technical concepts to other design peers in verbal and written form.
Education (One of the following is required)
A bachelor s in electrical engineering or related discipline plus 9 years of experience.
A master s in electrical engineering or related discipline plus 7 years of experience
Experience Required :
10 to 15 Years
Vacancy :
2 - 4 Hires
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