Principal Engineer - Design Verification Job in Spectrum Consultants India Pvt Ltd
Principal Engineer - Design Verification
Spectrum Consultants India Pvt Ltd
4+ weeks ago
- Hyderabad, Telangana
- Not Disclosed
Job Summary
Principal Engineer - Design Verification
Our vision is to transform how the world uses information to enrich life and our commitment to people, innovation, tenacity, collaboration, and customer focus allows us to fulfill our mission to be a global leader in memory and storage solutions. This means conducting business with integrity, accountability, and professionalism while supporting our global community.
As a Principal Design Verification Engineer., you will be responsible for logic design verification of our non-volatile memory designs, including advanced 3D NAND and other new technologies.
Responsibilities include, but not limited to:
Development of NAND Flash behavioural models in system Verilog
Should be able to lead/mentor the team
Complete verification on NAND Flash models based on design datasheet.
Technical support to internal and external model users
Collaboration with Application engineers on design datasheet and model requirements
Full-chip functional verification on non-volatile memory design projects
You thoroughly understand design specs and develop verification plans for various designs.
Test Bench Development in system Verilog targeting complete functionality coverage.
Support of system Verilog assertion and coverage-driven methodology
Support of design verification methodology improvements
Run directed and constrained-random verification tests.
You will think through design corner cases and be able to write relevant cover points.
Collaborate with digital design team to debug test cases and deliver functionally accurate designs.
Close coverage measures to identify verification holes and to show progress towards tape-out.
Minimum Qualifications:
MS or BS degree in Electrical or Computer Engineering or equivalent
8+ years of experience developing verification collateral in Verilog, System Verilog and UVM
UVM Proficiency is required
Prior work experience with complex coverage driven random constraint UVM environments.
Putting together complex UVM environments from scratch is a requirement.
Deep knowledge on circuit design, digital logic, and logic verification methodology
Understanding on Verilog RTL coding, System Verilog object-oriented language
Good knowledge on programming language such as C++, and scripting language like TCL and PERL
Preferred Skills:
Knowledge of Non-volatile memory design is highly desired.
Strong communication skills both written and verbal.
Strong interpersonal skills and maintain positive relationships.
Ambitious and goal-oriented
Collaborate effectively in a dynamic team environment.
Our vision is to transform how the world uses information to enrich life and our commitment to people, innovation, tenacity, collaboration, and customer focus allows us to fulfill our mission to be a global leader in memory and storage solutions. This means conducting business with integrity, accountability, and professionalism while supporting our global community.
As a Principal Design Verification Engineer., you will be responsible for logic design verification of our non-volatile memory designs, including advanced 3D NAND and other new technologies.
Responsibilities include, but not limited to:
Development of NAND Flash behavioural models in system Verilog
Should be able to lead/mentor the team
Complete verification on NAND Flash models based on design datasheet.
Technical support to internal and external model users
Collaboration with Application engineers on design datasheet and model requirements
Full-chip functional verification on non-volatile memory design projects
You thoroughly understand design specs and develop verification plans for various designs.
Test Bench Development in system Verilog targeting complete functionality coverage.
Support of system Verilog assertion and coverage-driven methodology
Support of design verification methodology improvements
Run directed and constrained-random verification tests.
You will think through design corner cases and be able to write relevant cover points.
Collaborate with digital design team to debug test cases and deliver functionally accurate designs.
Close coverage measures to identify verification holes and to show progress towards tape-out.
Minimum Qualifications:
MS or BS degree in Electrical or Computer Engineering or equivalent
8+ years of experience developing verification collateral in Verilog, System Verilog and UVM
UVM Proficiency is required
Prior work experience with complex coverage driven random constraint UVM environments.
Putting together complex UVM environments from scratch is a requirement.
Deep knowledge on circuit design, digital logic, and logic verification methodology
Understanding on Verilog RTL coding, System Verilog object-oriented language
Good knowledge on programming language such as C++, and scripting language like TCL and PERL
Preferred Skills:
Knowledge of Non-volatile memory design is highly desired.
Strong communication skills both written and verbal.
Strong interpersonal skills and maintain positive relationships.
Ambitious and goal-oriented
Collaborate effectively in a dynamic team environment.
Experience Required :
8 to 12 Years
Vacancy :
2 - 4 Hires
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