Analog Layout Engineer Job in Spectrum Consultants India Pvt Ltd
Analog Layout Engineer
Spectrum Consultants India Pvt Ltd
4+ weeks ago
- Bengaluru, Bangalore Urban, Karnataka
- Not Disclosed
Job Summary
What will you be doing in this role?
You will be responsible for working on layout development of high performance, high voltage analog blocks & ICs.
Work closely with Analog designer to understand the function of the block to make sure the layout brings the best for a given circuit design
Exercising right balance of area, performance and schedule during layout development
Learn about cross sections of components, new tools and methodology improvements in layout to enable highest levels of quality & efficiency
Learn Electro Migration, ESD/LU performance and layout parasitic
What do we expect from you?
Proficiency in Tools:
o Fully conversant with Virtuoso LE/XLS, Assura/Calibre/Hercules for verification and extraction, basic knowledge of perl/skill/shell scripting desirable.
o Must have done few blocks from floorplan to tape-out/PG.
Knowledge of Layout Basics:
o Block/Top level Layout (Floor planning, Power Planning, Bump planning, Clock route planning)
o Device Layout (Knowledge of best layout practices for minimizing impacts of process mismatches through various matching techniques like common centroid, inter-digitation, addition of dummies etc, matching vs. area tradeoffs, best practices for BJTs, MOS, Resistor layout. Must have completed the layout of basic building blocks like BG, TSD, POR, Oscillators, LDO, IOs etc)
o Interconnect Design (Techniques for EM & IR Drop mitigation, Parasitics minimization, Matching for R/L/C, Crosstalk Mitigation through shielding/isolation etc, Antenna Effect mitigation, Step Coverage/Density effect mitigation)
o HV, ESD & Latch-up (Knowledge of impact of bus resistances, ESD transistor/interconnect DRC, EM constraints, effective guard-ring techniques )
o DSM Effects (Knowledge of and techniques to mitigate proximity and strain effects like LoD, WPE)
o Noise (Knowledge of and techniques to reduce noise coupling and/or generation through Substrate taps, Guard rings, Shielding, Decoupling Caps, Bondwires, DNW Isolation, Substrate Coupling etc)
Behavioral:
o Excellent written and verbal communication skills and should be a good team player
o Demonstrates an attitude with highest levels of integrity and commitment to success. Every assignment small or big needs to be driven with a complete ownership mindset
Qualifications
Education: B.E./B.Tech (Desirable) or Diploma with Special Layout Training certification
You will be responsible for working on layout development of high performance, high voltage analog blocks & ICs.
Work closely with Analog designer to understand the function of the block to make sure the layout brings the best for a given circuit design
Exercising right balance of area, performance and schedule during layout development
Learn about cross sections of components, new tools and methodology improvements in layout to enable highest levels of quality & efficiency
Learn Electro Migration, ESD/LU performance and layout parasitic
What do we expect from you?
Proficiency in Tools:
o Fully conversant with Virtuoso LE/XLS, Assura/Calibre/Hercules for verification and extraction, basic knowledge of perl/skill/shell scripting desirable.
o Must have done few blocks from floorplan to tape-out/PG.
Knowledge of Layout Basics:
o Block/Top level Layout (Floor planning, Power Planning, Bump planning, Clock route planning)
o Device Layout (Knowledge of best layout practices for minimizing impacts of process mismatches through various matching techniques like common centroid, inter-digitation, addition of dummies etc, matching vs. area tradeoffs, best practices for BJTs, MOS, Resistor layout. Must have completed the layout of basic building blocks like BG, TSD, POR, Oscillators, LDO, IOs etc)
o Interconnect Design (Techniques for EM & IR Drop mitigation, Parasitics minimization, Matching for R/L/C, Crosstalk Mitigation through shielding/isolation etc, Antenna Effect mitigation, Step Coverage/Density effect mitigation)
o HV, ESD & Latch-up (Knowledge of impact of bus resistances, ESD transistor/interconnect DRC, EM constraints, effective guard-ring techniques )
o DSM Effects (Knowledge of and techniques to mitigate proximity and strain effects like LoD, WPE)
o Noise (Knowledge of and techniques to reduce noise coupling and/or generation through Substrate taps, Guard rings, Shielding, Decoupling Caps, Bondwires, DNW Isolation, Substrate Coupling etc)
Behavioral:
o Excellent written and verbal communication skills and should be a good team player
o Demonstrates an attitude with highest levels of integrity and commitment to success. Every assignment small or big needs to be driven with a complete ownership mindset
Qualifications
Education: B.E./B.Tech (Desirable) or Diploma with Special Layout Training certification
Experience Required :
1 to 3 Year
Vacancy :
2 - 4 Hires
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