Engineer Trainee Job in Smartdv Technologies India Private Limited

Engineer Trainee

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Job Summary
  • B.E or MTech from reputed university with 0-2 years experience.
  • Strong understanding of Digital design
  • Working experience with Verilog or VHDL or SystemVerilog
  • Experience in writing C or C++
  • Understanding of OOPS.
  • Knowledge of Perl or Python or TCL scripting languages
  • Very good academic track record
Experience Required :

0 to 2 Years

Vacancy :

2 - 4 Hires

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