ASIC ,Verilog, VHDL, R And D Engineer Job in Schindlers Incorporated

ASIC ,Verilog, VHDL, R And D Engineer

Schindlers Incorporated 4+ weeks ago

• Bengaluru, Bangalore Urban, Karnataka
• Not Disclosed
• Permanent
• Full-time

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Job Summary

Position : Rand D EngineerCompany : A SEICMM level 5 Software CompanyLocation : Bangalore.Skills :Minimum of 2 years experience in any of the following skills: VHDL/Verilog , ASIC Design Flow , Simulation Skills, Synthesis and Timing analysis , Logic Design, UnixC/C++ , Physical designEDA tools.

Minimum Requirements

Very good in Designing - ASIC ,Verilog / VHDL.Domain Experience in one of the areas like Memory Controller Design, Bus Interfaces.

Qualification

B.Tech/B.E.

Experience Required :

3 to 10 Years

Vacancy :

1 Hire

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