Smts/principal Asic Design Engineer- Csi/dsi Design And Integration Job in Marvylogic

SMTS/Principal ASIC Design Engineer- CSI/DSI Design and Integration

Job Description

• 10+ years of ASIC RTL Design experience and Verilog/System Verilog proficiency.
• Experience with multiple clock and power domains.
• Extensive experience in integration and validation of CSI/DSI/DPHY/CPHY/other MIPI cores (including controller and SerDes).
• Experience with CSI/DSI debug.
• RTL Design and implementation of CSI/DSI controllers.
• Create block-level micro-architecture specification and that outline interfaces, timing behavior, design tradeoffs, and performance goals.
• Review vendor IP integration guidelines and verify the compliance throughout the design flow.
• Run integrity check tools such as Lint/CDC/DFT/LEC/UPF to satisfy coding and implementation guidelines.
• Participate in design verification process by reviewing test plans, coverage reports, writing assertions and other design modifications to improve verification quality.
• Participate in physical implementation process by providing synthesis constraints, timing exceptions and making design updates to meet area, power and performance goals.

Responsibilities

• Be able to work and communicate with multi-site teams
• Responsible for the review of FPGA netlist releases (block/chip)
• ASIC product life cycle experience (requirements, design, implementation, test and post-silicon validation)