Physical Design Lead Job in Invecas

Hands on experience with Implementation (PnR & Signoff) of multimillion gate SoC designs in cutting edge process technologies (40nm, 28nm, 16nm, 10nm)

• Lead all aspects of SoC Physical Design with strong expertise in the area of chip/partition floor-planning, design partition creation, budgeting and feedthrough planning
• Work alongside RTL/Synthesis/DFT teams to define design partitions and create floorplan as per the design data flow
• Work closely with library, technology and Analog IP teams for physical design requirements
• Work closely with CAD teams and involve in methodology development and improvement
• Own SoC/partition physical design activities while managing a team of 4-5 engineers

Desired Skills and Experience:

• B. Tech. / M. Tech. with 5-12 years of experience in Physical Design
• The candidate should be able to work with and lead a team of engineers on all aspects of Physical Design tasks on an SOC design
• Should have handled Netlist to GDS II implementation at Chip/partition level for atleast 2-3 designs
• Hands-on expertise with technology nodes like 28nm, 16nm and below
• Good knowledge of EDA tools from Synopsys, Cadence and Mentor, particularly with ICCII & Calibre
• Excellent understanding of design partitioning & budgeting along with hands-on experience in Chip/partition floor planning, placement optimizations, Clock planning and routing.
• Good understanding of low power implementation techniques and static low power checks
• IO ring design and bump planning is a plus
• Being proficient in TCL, Perl scripting is a plus