Memory Layout Engineer Job in Invecas

• Responsible for creating digital IP to enable layout work in new technology: PCELL creation, SRAM leaf cells, Productivity Scripts.
• Responsible for analysis of new technology and translating into guidelines for EMIR, SRAM layout guidelines etc.
• Review layouts for area/power/quality and post layout activities.
• Experience in handling of different types of memory architecture.
• Power and signal route planning.
• Block and top level layouts, integration and validations.
• Floor plan and integration of major layout modules.

Desired Skills and Experience:

• You would need to have sound fundamentals in CMOS devices, basics of VLSI design.
• Proven project cycle and tape out experience in SRAM memory layout design.
• Proficiency in Perl/Python or equivalent scripting language.
• Good interpersonal skills, should be an excellent teammate.
• BE/M-Tech in Electrical & Electronics or equivalent.