Sr. ASIC Design Engineers Job in Deeva Networks

Design and implement IP blocks for SOC. Specific application areas would include Video Processor, Traffic Managers, Memory controller, Ethernet, Bus Interfaces like PCI Express, PCI-X and PCI.In this position the candidate will be responsible for Macro and Micro architecture development, RTL design, Logic verification, Synthesis and timing verification. They will also mentor and guide junior engineers.RequirementBSEE or MSEE or equivalent from reputed universities with over 5 years experience in ASIC design Experience in RTL logic design using verilog and industry standard tools EDA tools such Synopsys Design Compiler, Modelsim, NC-SIM etc. Modeling hardware algorithms using C. Experience with complete FPGA and ASIC Flows involving timing closure of High Speed Digital Design Using scripting languages and design automation Good communication and interpersonal skills and team motivator and team player. Experience - 5 to 10 yearsJob location - Pune

Minimum Requirements

Details required from your end: - Reason for change Current and expected salary Notice period Willingness to relocate to Bangalore Date of Birth Passport Number Any alternate contact numberPlease reply ASAP. P.S.: IF any friend or colleague of yours suits the profile and is looking for a change please ask them to forward their resumes on the same id.

B.Tech/B.E., M.Tech