Senior Design Engineer Rtl / Soc Job in Coreel Technologies

Senior Design Engineer Rtl / Soc

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Job Summary

Education Qualification: BE/B.Tech in E&C

Total Experience: 3 Years to 5 Years

Primary Skills

1. DSP algorithms in FPGA environment for Radar and Electronic Warfare systems.
2. Interact with SW and HW teams to define the architecture/system partioning and lead a team of FPGA engineers to deliver the solutions.
3. Proficient in VHDL & Xilinx FPGAs.
4. FPGA development flow: micro-architecting, RTL coding, Synthesis & implementation flow, verification and validation.

Experience Required :

Fresher

Vacancy :

2 - 4 Hires

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