Gdc In Design Center - Asic Verification Engineer 1 Job in Atos

Gdc In Design Center - Asic Verification Engineer 1

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Job Summary
  • Curious, demanding and rigorous.
  • Mastering object oriented programming.
  • Knowledge of UVM verification methodology (or equivalent) and SystemVerilog / SystemC hardware verification languages ??
  • Knowledge of Constraint-Random / Coverage-Driven verification environments development in SystemVerilog / C ++ (drivers / monitors, constraint random tests, checkers and self-checking models and coverage models written in SystemVerilog-Covergrourp / SVA)
  • Knowledge of simulation tools and coverage database visualization tools
  • Effective in problems solving by rapidly identifying their root cause and developing patches or workarounds under tight timing constraints
Experience Required :

Fresher

Vacancy :

2 - 4 Hires

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